This application is based on and claims the benefit of priority from the prior Japanese Patent Application No. 2001-052588, filed on Feb. 27, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates generally to a semiconductor device having a voltage regulator for output of a regulated voltage that is variable in response to an output voltage of an internal voltage generation circuit.
2. Description of the Related Art
Prior known electrically rewritable non-volatile semiconductor memory devices include electrically erasable programmable read-only memory (EEPROM) chips, also known as xe2x80x9cFlashxe2x80x9d memories in the semiconductor device art. Currently available Flash EEPROM chips come with an array of rows and columns of nonvolatile memory cells, each of which is typically formed of a metal insulator semiconductor field effect transistor (MISFET) of the so-called xe2x80x9cstack gatexe2x80x9d structure with a floating gate and a control gate being stacked above a semiconductor chip substrate. Each stack-gate MISFET memory cell stores therein a digital binary data bit of a logic xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d in accordance with the charge accumulation state of its floating gate. One example is that a storage data bit is assumed to be a logic xe2x80x9c0xe2x80x9d in the event that the floating gate storing thereon electrons is high in threshold voltage while letting the bit be a logic xe2x80x9c1xe2x80x9d when the floating gate releases the electrons and thus is low in threshold voltage.
Flash memories include EEPROMs of the NOR type. In the case of such NOR-EEPROMs, a memory cell array is arranged so that a respective one of rows of memory cells is associated with a corresponding one of parallel bit lines in a manner such that drains of these cells are connected together or xe2x80x9ccommon-coupledxe2x80x9d to the bit line whereas each column of memory cells is common-coupled at control gates to a corresponding one of parallel word lines that cross over the bitlines. A data write operation is performed after having erased all the cells of the memory array at a time, known as xe2x80x9call-at-a-timexe2x80x9d or xe2x80x9call-at-oncexe2x80x9d erase among those skilled in the art. The all-at-once erase is achievable in a way as follows. Firstly all the wordlines of the memory cell array are applied a voltage of the negative polarity having a specific potential levelxe2x80x94typically, xe2x88x927 volts (V), or more or less. Then, apply a positive voltage of about +10V to a common source, causing electrons presently residing on floating gates to release toward the substrate side by Fowler-Nordheim (F-N) tunneling effects. Whereby, all the memory cells are thus set in the erase state of data xe2x80x9c1.xe2x80x9d
Data writing on a per-cell basis is done by applying a write voltage of about 10V to a word line being presently selected from among the wordlines and then giving to the selected bitline either one of an on-chip power supply voltage Vdd and a source or xe2x80x9cgroundxe2x80x9d voltage Vss in a way depending on whether the data being written is a logic xe2x80x9c0xe2x80x9d or xe2x80x9c1.xe2x80x9d This voltage application results in that in a cell to which logic xe2x80x9c0xe2x80x9d data is given, xe2x80x9chotxe2x80x9d electrons are injected into the floating gate thereof causing its threshold voltage to shift or xe2x80x9coffsetxe2x80x9d in a positive direction. In the case of logic xe2x80x9c1xe2x80x9d data, no appreciable threshold voltage changes occur.
Data read is done by giving a read voltage to a selected wordline and then detecting the presence or absence of a cell current flow.
In the above operations, the data write is typically combined with a verify-read operation for confirmation or verification of the resulting write state. More specifically, after having written data under application of the write voltage, the verify-read operation is done. Repeated execution of such write voltage application and its following verify-read session forces the threshold voltage of a written memory cell to finally fall within a prespecified distribution range. Similarly in the case of data erase, recurrent execution of erase voltage application and its following erase-verify operation enables the threshold voltage of an erased cell to finally fall within a specified distribution range.
For adequate control of the above-noted operations in the write and erase modes, a need is felt to supply a stabilized and regulated voltage with its potential optimized on a per-mode basis. A presently available approach to generating such a regulated voltage is to employ a voltage regulator with an ability to generate a plurality of types of regulated voltages based on an output voltage of potential rise-up or xe2x80x9cboosterxe2x80x9d circuitry for use as an internal power supply. A scheme using this approach is disclosed, for example, in J. F. Dickson, xe2x80x9cOn-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 3, June 1976 at pp. 374-378. Another technique is taught from A. Umezawa et al., xe2x80x9cA 5V-Only Operation 0.6 xcexcm Flash EEPROM with Row Decoder Scheme in Triple-Well Structure,xe2x80x9d IEEE J. Solid-State Circuits, Vol. 27, No. 11, November 1992, pp. 1540-1546.
See FIG. 18. This diagram shows an arrangement of one prior art voltage regulator adaptable for use with Flash EEPROM chips. This regulator shown herein includes a driver unit 1. The driver 1 has a serial connection of MOS transistors: a PMOS transistor QP2 for potential pull-up drive, and an NMOS transistor QN2 for pull-down drive. The pull-up PMOS transistor QP2 has a source, to which a potentially increased or xe2x80x9cboostedxe2x80x9d voltage Vpp as output from a potential booster circuit (not shown) is supplied. The pull-down NMOS transistor QN2 has its source which is coupled to ground. These transistors QP2, QN2 are coupled together at a connection node N0, which is for use as an output terminal of a regulated voltage Vreg.
An operational amplifier OP1 is provided for controlling a gate of the pull-down NMOS transistor QN2. It is an ensemble of operational amplifier OP2 and NMOS transistor QN1 plus PMOS transistor QP1 that controls a gate of the pull-up PMOS transistor QP2. The NMOS transistor QN1 is operable under control of an output of the op-amp OP2. The PMOS transistor QP1 functions as a current source load of NMOS transistor QN1. PMOS transistors QP1, QP2 make up a current mirror circuit.
The regulator of FIG. 18 has its output node N0, at which a voltage division circuit 2 is provided. This voltage divider circuit 2 includes a serial combination of resistors R1 to R3 and a switch element formed of an NMOS transistor QN3. Connected to a connection node N2 of the resistors R2-R3 is an NMOS transistor QN4 which operates under control of a write-use control signal PROG for coupling the node N2 to ground. NMOS transistor QN3 has its gate which is to be controlled by a verify-read control signal VRFY. When NMOS transistor QN3 is driven to turn on, a connection node N3 of resistor R3 and NMOS transistor QN3 is grounded.
One of the op-amps OP1-OP2xe2x80x94here, opamp OP2xe2x80x94is given a reference voltage Vref at its non-inverting input terminal, with a voltage potential at node N1 being fed back to an inverting input terminal thereof. The other opamp OP1 is such that the reference voltage Vref is given to its inverting input terminal while a potential at node N1 is fed back to its non-inverting input terminal.
This regulator experiences application of feedback control in a way such that the node N1 of voltage divider 2 becomes equal in potential to the reference voltage Vref being supplied to the opamps OP1-2 whereby it outputs a potentially regulated voltage Vreg with potential xe2x80x9ctrackabilityxe2x80x9d to a change in boosted output voltage Vpp. More specifically, while the potentially divided output voltage that is obtainable at the node N1 of voltage divider 2 stays lower than the reference voltage Vref, the opamp OP1 derives its output voltage of high level causing NMOS transistor QN1 to turn on whereas an output of opamp OP1 is at low level letting NMOS transistor QN2 turn off. This results in the current mirror circuit of PMOS transistors QP1-2 permitting a pull-up current Iup to flow in pull-up PMOS transistor QP2, thereby forcing the regulated voltage Vreg obtained at output node N0 to increase in potential.
When the regulated voltage Vreg potentially rises up causing the voltage at voltage divider node N1 to become higher than the reference voltage Vref, the opamp OP2""s output drops down at low level, letting NMOS transistor QN1 turn off. Simultaneously the opamp OP1""s output becomes high level, causing NMOS transistor QN2 to turn on. This precludes flow of the pull-up current Iup while alternatively allowing a pull-down current Idn to flow in pull-down NMOS transistor QN2. This results in a likewise decrease in the regulated voltage Vreg. With the above-stated feedback control operation, there is obtainable the regulated voltage Vref that is stabilized at a preselected potential level lower than the boosted output voltage Vpp.
The stabilization level of the regulated voltage Vreg is variable at different levels depending upon whether each of the write control signal PROG and verify-read control signal VRFY is presently set at either xe2x80x9cHighxe2x80x9d (xe2x80x9cHxe2x80x9d) level or xe2x80x9cLowxe2x80x9d (L) level. This can be said because the voltage divider 2 must differ in potential division ratio in light of the fact that when the write control signal PROG stays at xe2x80x9cHxe2x80x9d and verify-read control signal VRFY is at xe2x80x9cL,xe2x80x9d node N2 is grounded and, alternatively, when the former is at xe2x80x9cLxe2x80x9d and the latter is at xe2x80x9cH,xe2x80x9d node N3 is grounded.
Practically, a write operation of an EEPROM chip using the FIG. 18 circuitry is as follows. When the write control signal PROG potentially goes high to reach xe2x80x9cHxe2x80x9d level, the boosted output voltage Vpp begins to rise up in potential. This potential increase permits a pull-up current Iup to flow in pull-up PMOS transistor QP2. Thus the regulated voltage Vreg at regulated voltage output node N0 behaves to potentially increase with an increase in the boosted voltage Vppxe2x80x94say, the former xe2x80x9ctracksxe2x80x9d the latter. The required write voltage is thus obtained, which is well stabilized at a level of Vreg=7V, for example. After elapse of a xe2x80x9cfixedxe2x80x9d length of time, the write control signal PROG goes low to xe2x80x9cLxe2x80x9d level and the verify control signal VRFY goes high at xe2x80x9cHxe2x80x9d level. This forces node N3 to be grounded. Whereby, the regulated voltage Vreg is such that a lower level becomes a point of stabilization. Thus a verify-read voltage of for example about Vreg=5V is obtained.
With the voltage regulator shown in FIG. 18, in cases where the opamps OP1-2 have xe2x80x9cidealxe2x80x9d characteristics with no appreciable input offsets, the resulting pull-up and pull-down currents Iup, Idnxe2x80x94these are derived from the driver 1""s PMOS transistor QP2 and NMOS transistor QN2 respectivelyxe2x80x94vary with a change in potentially divided output voltage VN1 of the divider circuit node N1 in a pattern as demonstrated in FIG. 19A. The current-versus-voltage characteristic of FIG. 19A indicates the state that a penetration current Ion occurring due to simultaneous turn-on of these transistors QP2, QN2 stays less. In contrast, when opamps OP1-2 are relatively large in input offset, a large penetration current Ion can flow therein as shown in a characteristic diagram of FIG. 19B.
This penetration current would result in an increase in power consumption or dissipation of integrated circuits concerned. Another problem faced with the prior art is that the flow of larger penetration current in booster circuitry badly behaves to limit the performance of the booster, i.e. voltage boost ability or xe2x80x9cboostability,xe2x80x9d in view of the fact that most booster circuits for generation of the boosted voltage Vpp are less in current supplying abilities. The limitation to boostability in turn leads to an increase in time as taken to create the boosted voltage Vpp and regulated voltage Vreg with potential trackability thereto. In the worst case, any desired regulated voltages will no longer be obtainable in any way.
A semiconductor device in accordance with one aspect of this invention has a voltage regulator for outputting a regulated voltage potentially varying in response to an output voltage of an internal voltage generation circuit. The voltage regulator includes: a driver including a pull-up transistor and a pull-down transistor serially connected between an output node of the internal voltage generation circuit and a reference potential terminal, for outputting a regulated voltage at its regulated voltage output node corresponding to the connection node of the pull-up and pull-down transistors; a voltage divider circuit configured to potentially subdivide the regulated voltage output at the regulated voltage output node; a first operational amplifier configured to control current drivability of the pull-down transistor in accordance with a difference between a first reference voltage and a divided output voltage of said voltage divider circuit; and a second operational amplifier configured to control current drivability of the pull-up transistor in accordance with a difference between a second reference voltage and the divided output voltage of the voltage divider circuit in such a way as to vary in a reverse direction to the current drivability of the pull-down transistor.